According to the inventor's study, there are techniques of the transceiver stated below.
For example, JP-T No. 11(1999)-511926 discloses a technique of a phase matching circuit in which a synchronization signal that is lower in frequency than a clock signal is superimposed on respective data signals that are transmitted from a transmitter to a receiver in parallel. In the technique, a phase relationship between the respective parallel data signals can be held without causing an increase in the transmission speed of the parallel data signal or an increase in the number of signal lines between the transmitter and the receiver.
Also, JP-A No. 2005-151410 discloses a multi-channel data transmission technique by which the contiguous encoded signal of plural channels are received and then converted into a pair of synchronous binary characters to prevent an influence of skew.
Also, U.S. Pat. No. 4,486,739 discloses a technique of 8B10B that converts parallel data of 8 bits into contiguous data of 10 bits.